Title :
Defect-oriented analysis of memory BIST tests
Author_Institution :
HPL Inc., San Jose, CA, USA
Abstract :
This paper describes a defect-oriented analysis of 4 BIST tests that are used to test a commercial 6-port embedded SRAM. We will examine the realistic fault and defect coverages of these memory BIST tests. We also uncover the subtle effect that addressing order has on the coverage that a test can provide. In addition, we will show that the coverage that a test provides can vary from row to row depending on the addressing scheme.
Keywords :
SRAM chips; built-in self test; design for testability; embedded systems; fault simulation; integrated circuit testing; 6-port embedded SRAM; Safari system; Venn diagram; addressing order; analog transistor-level simulation; defect coverages; defect-oriented analysis; design for test; fault coverages; inductive fault analysis; memory BIST tests; memory test quality; realistic faults; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit faults; Computational modeling; Fault detection; Power supplies; Read-write memory; Semiconductor device testing; System testing;
Conference_Titel :
On-Line Testing Workshop, 2002. Proceedings of the Eighth IEEE International
Print_ISBN :
0-7695-1641-6
DOI :
10.1109/OLT.2002.1030219
