A silicon-based yield gain evaluation methodology for embedded-SRAMs with different redundancy scenarios

Yield improvement is an essential issue for modern high-volume manufacturing CMOS processes. Process yield is particularly low for area-critical designs, such as embedded memories. The use of redundancy structures which replace faulty memory locations with good ones, has a direct impact on the final chip yield. This paper describes an experimental methodology employed to evaluate the yield gain associated with different redundancy approaches and shows how this method can be applied to determine the optimal redundancy configuration which maximizes the number of good dies per wafer, depending on the embedded memory requirements of a specific product.