Title :
Application-Specific RISC Architecture for ITU-T G.729 Decoding Processing
Author :
Wu, Chien-Hsuan ; Huang, Chin-Yu ; Chang, Jun-Ru
Author_Institution :
Product Value Lab., Acer Comput. Corp., Taipei
Abstract :
In this paper, we propose a new application-specific RISC processor architecture to overcome the performance bottleneck of traditional RISC processor executing complex speech decoding application such as, what we mostly concern about, ITU-T G.729 decoder. By introducing the enhanced hardware components into ARM v4 processor architecture, the new application-specific instructions are accomplished and the performance of this new architecture is about 52% improvement than original ARM v4 processor architecture
Keywords :
application specific integrated circuits; autoregressive moving average processes; decoding; integrated circuit design; microprocessor chips; reduced instruction set computing; speech coding; ARM v4 processor architecture; ITU-T G.729 decoder; application-specific RISC processor architecture; hardware component; Algorithms; Computer architecture; Design methodology; Finite impulse response filter; Hardware design languages; Iterative decoding; Oral communication; Reduced instruction set computing; Speech processing; Speech synthesis;
Conference_Titel :
TENCON 2006. 2006 IEEE Region 10 Conference
Conference_Location :
Hong Kong
Print_ISBN :
1-4244-0548-3
Electronic_ISBN :
1-4244-0549-1
DOI :
10.1109/TENCON.2006.344183
