A Low Power Pipeline A/D Converter by Using Double Sampling and Averaging Techniques

A 1.8 V, 10-Bit, 40-MS/s pipeline analog-to-digital converter designed using 0.18-mum CMOS technology is presented. The new structure of the A/D converter is based on double sampling and averaging techniques. By the first technique, all the stage amplifiers are active at the both sampling and holding cycles. Averaging as the second technique minimizes the capacitance mismatch and exchanges the priority of input-referred noise and capacitance mismatch in the selection of the stage caps. The converter achieved a peak spurious-free-dynamic-range of 61 dB, maximum differential nonlinearity 0.5 of least significant bit (LSB), maximum integral linearity of 0.9 LSB, and power consumption of 5 mW