DocumentCode :
2204034
Title :
Finite automata and badly timed elements
Author :
McNaughton, Robert
fYear :
1963
fDate :
28-30 Oct. 1963
Firstpage :
117
Lastpage :
130
Abstract :
This paper summarizes some rather extensive research on the problem of constructing logic nets out of elements whose timing causes trouble either in their slowness or in their lack of precision. The problem is made precise by setting up a theory of logic nets that is abstract but realistic. Its abstractness consists in its lack of similarity to any particular hardware, and in its strictly mathematical formulation, which leaves many engineering problems out of consideration. Its realism consists in its adherence to several stipulations: (S1) There is an upper bound on the fan-in and fan-out of any element. (S2) There is an upper bound on the number of elements that can occupy a given area or volume of space. (S3) There is an upper bound on the distance between two elements that are directly connected together. (S4) There is a lower bound, greater than zero, on the time of operation of any element. (S5) The timing of any element is not precisely predictable; all that is known about how long it will take to switch is an upper bound and a lower bound; beyond this knowledge, the timing is not even statistically predictable. There is theoretical justification in our having assumed, unrealistically that elements never malfunction or wear out. The theory affords a way of constructing, with a constant repetition rate, all finite automata as asynchronous nets that will withstand a worst-case analysis. Similar work by others is compared.
Keywords :
Automata; Circuit synthesis; Hardware; History; Logic; Sequential circuits; Signal synthesis; Switches; Timing; Upper bound;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Switching Circuit Theory and Logical Design, Proceedings of the Fourth Annual Symposium on
Conference_Location :
Chicago, IL, USA
Type :
conf
DOI :
10.1109/SWCT.1963.5
Filename :
4569792
Link To Document :
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