DocumentCode :
2204439
Title :
A review of logic synthesis techniques for beginning VHDL designers
Author :
Bien, Y. Kevin ; Perry, Reginald J. ; Arora, Krishna
Author_Institution :
Coll. of Eng., Florida A&M Univ., Tallahassee, FL, USA
fYear :
1996
fDate :
11-14 Apr 1996
Firstpage :
541
Lastpage :
544
Abstract :
The electronics industry has adopted hardware description languages (HDLs) as a method to manage complex application specific integrated circuit (ASIC) designs. However, ambiguous code and inappropriate usage of HDL syntax may restrict an IC design engineer´s ability to fully exploit the advantages offered by HDLs and logic synthesis tools. This paper briefly reviews many common mistakes made by beginning VHDL designers and provides several suggestions for improving their coding techniques
Keywords :
application specific integrated circuits; circuit layout CAD; electronics industry; hardware description languages; logic CAD; ASIC design; VHDL; application specific integrated circuit; coding techniques; electronics industry; hardware description languages; logic synthesis techniques; logic synthesis tools; Application specific integrated circuits; Computer aided engineering; Counting circuits; Design engineering; Educational institutions; Electronics industry; Engineering management; Hardware design languages; Integrated circuit synthesis; Logic design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Southeastcon '96. Bringing Together Education, Science and Technology., Proceedings of the IEEE
Conference_Location :
Tampa, FL
Print_ISBN :
0-7803-3088-9
Type :
conf
DOI :
10.1109/SECON.1996.510131
Filename :
510131
Link To Document :
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