High-efficiency low-power one-clock solutions for multi-clock chips and systems

Author

Fried, Rafael

Author_Institution

Dept. of Electr. Eng., Swiss Federal Inst. of Technol., Lausanne, Switzerland

fYear

1996

fDate

13-14 Sep 1996

Firstpage

60

Lastpage

65

Abstract

This paper presents two basic high-efficiency low-power approaches for driving multi-clock chips and systems from only one external clock source. In the first approach a high-frequency crystal oscillator with reduced power-consumption is used to generate all the system frequencies. For the second approach, a low-power Digital Phase Locked Loop (DPLL) with +/- 100 ps jitter, one-cycle frequency lock-in time and very high frequency multiplication factor is presented

Keywords

crystal oscillators; digital integrated circuits; digital phase locked loops; digital systems; jitter; timing circuits; digital PLL; external clock source; high-frequency crystal oscillator; low-power DPLL; low-power one-clock solutions; multi-clock chips; multi-clock systems; power-consumption reduction; Clocks; Digital signal processing chips; Electromagnetic interference; Embedded system; Frequency conversion; Jitter; Oscillators; Personal communication networks; Phase locked loops; Power generation; Stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Analog and Mixed IC Design, 1996., IEEE-CAS Region 8 Workshop on

Conference_Location

Pavia

Print_ISBN

0-7803-3625-9

Type

conf

DOI

10.1109/AMICD.1996.569385

Filename

569385