DocumentCode
2204514
Title
On the minimum stage realization of switching functions using logic gates with limited fan-in
Author
Hicks, G.L. ; Bernstein, A.J.
fYear
1964
fDate
11-13 Nov. 1964
Firstpage
149
Lastpage
155
Abstract
In this paper a method is presented for reducing the number of stages of logic in the realization of an arbitrary Boolean function when an upper bound exists on the fan-in at each gate. A procedure for obtaining the minimum stage realization of the function in sum of products form is first developed. The use of factoring to reduce the number of stages below this minimum is then described.
Keywords
Arithmetic; Boolean functions; Delay; Digital systems; Laboratories; Logic circuits; Logic gates; Minimization; Switching circuits; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Switching Circuit Theory and Logical Design, 1964 Proceedings of the Fifth Annual Symposium on
Conference_Location
Princeton, NJ, USA
Type
conf
DOI
10.1109/SWCT.1964.21
Filename
4569816
Link To Document