Title :
High performance logic technology-scaling trend and future challenges
Abstract :
The 130 nm Si logic technology is the latest generation being ramped in production on both 200 mm and 300 mm wafers. This technology employs CMOS transistors with physical gate length of 70 nm, physical gate dielectric thickness of 1.5 nm, and full Cu multi-level interconnect for high performance. As the minimum dimension approaching atomic scale, breakthroughs are required to maintain the scaling trend. In this paper, requirements and solution paths for scaling CMOS based logic technology beyond 70 nm generation node (<40 nm in physical gate length) have been investigated using a combination of simulation, experimentation, and critical analysis. Conclusions are presented
Keywords :
CMOS logic circuits; integrated circuit interconnections; integrated circuit manufacture; nanotechnology; technological forecasting; 130 nm; CMOS transistors; atomic scale; design rules; full Cu multilevel interconnect; high performance logic technology; interconnect RC increase; interconnect aspect ratio; physical gate length; process challenges; scaling trend; simulation; volume production; Analytical models; CMOS logic circuits; CMOS technology; Delay; Dielectrics; Frequency; Isolation technology; MOSFETs; Production; Transistors;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6520-8
DOI :
10.1109/ICSICT.2001.981425
