Super-Systolic Array for 2D Convolution

This paper proposes a bit-level super-systolic array for 2D convolution which needs 1-bit ports for each input or output sequence. In addition to the arrangement of delays for data flow synchrony, the super-systolic array in which the cell of systolic array is organized again as a systolic array is adopted to perform the bit-level data flow and operation on bit data. The derived super-systolic array for 2D convolution is synthesized using Synopsys design compiler based on Hynix 035 mum cell library and compared with conventional word-level systolic array for 2D convolution. The bit-level super-systolic design is very compact in that it needs only 1-bit ports for each I/O sequence instead of n-bit ports in word-level design besides the reduced area requirement without time penalty on the output