Title :
A multiple-valued single-electron SRAM by the PADOX process
Author :
Inokawa, Hiroshi ; Fujiwara, Akira ; Takahashi, Yasuo
Author_Institution :
NTT Basic Res. Labs., NTT Corp., Kanagawa, Japan
Abstract :
Multiple-valued static memory consisting of a single-electron transistor (SET) and a MOSFET is proposed. The memory operation is verified by using transistors fabricated by the CMOS-compatible pattern-dependent oxidation (PADOX) process. The results indicate that a dramatic increase of CMOS memory density can be attained by the use of a SET with multiple-valued capability
Keywords :
CMOS memory circuits; MOSFET; SRAM chips; integrated circuit measurement; single electron transistors; CMOS memory density; CMOS-compatible pattern-dependent oxidation process; MOSFET; PADOX process; SET; memory operation; multiple-valued capability transistor; multiple-valued single-electron SRAM; multiple-valued static memory; single-electron transistor; transistors; Capacitance; Circuit stability; MOSFET circuits; Nonvolatile memory; Oxidation; Random access memory; Silicon on insulator technology; Single electron transistors; Voltage; Wire;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6520-8
DOI :
10.1109/ICSICT.2001.981456
