A flexible SRAM compiler for embedded application

Author

Liu, Yong ; Gao, Zhiqiang

Author_Institution

Inst. of Electron., Tsinghua Univ., Beijing, China

Volume

1

fYear

2001

fDate

2001

Firstpage

213

Abstract

SRAM compiler uses predefined building blocks or leaf cells and connectivity information to compile SRAMs of user-specified size. In this paper a high-speed embedded SRAM compiler is described. It is based on TSMC´s 0.5 μm CMOS process. It can compile both single-port and dual-port SRAMs. SRAM is a completely synchronous architecture with a maximal capacity 16 k* 64=1 Mb bits. The compiler generates the layout, behavioral level models, schematic symbols, and a layout abstraction to place and route. The program in Skill language can automatically complete the creation of all the models in different levels. The SRAM compiler has a friendly user interface. Users can specify the necessary parameters and then get all the results. The SRAM compiler can be easily integrated into Cadence and other CAD frameworks

Keywords

CMOS memory circuits; SRAM chips; integrated circuit layout; 0.5 micron; 1 Mbit; CAD frameworks; CMOS process; Cadence; Skill language; behavioral level models; connectivity information; dual-port SRAMs; embedded application; flexible SRAM compiler; high-speed embedded SRAM compiler; layout; layout abstraction; leaf cells; predefined building blocks; schematic symbols; single-port SRAMs; synchronous architecture; Application specific integrated circuits; CMOS process; Communication system control; Decoding; Design automation; Digital signal processing chips; Random access memory; Semiconductor device modeling; Testing; User interfaces;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6520-8

Type

conf

DOI

10.1109/ICSICT.2001.981458

Filename

981458