Title :
A low power 10-bit 300 kS/s RSD coded pipeline A/D-converter
Author :
Mantyniemi, Antti ; Rahkonen, Timo ; Ruha, Antti
Author_Institution :
Dept. of Electr. Eng., Oulu Univ., Finland
Abstract :
This paper describes a 10-bit 300 kS/s analog-to-digital converter fabricated in a 0.8-μm CMOS technology. The main objective was to minimise the power consumption of the circuit. This was achieved by using an interleaved pipeline structure with only one operational amplifier per stage. The current consumption of the converter circuit is 2 mA from 2.7 V power supply when using a power saving scheme in which the resolution per stage is moderately relaxed towards the LSB. The digital RSD (Redundant Signed Digit) principle is used to correct the errors caused by the mismatch in the gain factor 2 and the comparator offsets. The measured SNR was 58.5 dB, ENOB 9.4 bits, typical INL +/-1.5 LSB and DNL +/-0.5 LSB. The active chip area is 1.3 mm2, excluding pads
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); operational amplifiers; pipeline arithmetic; redundant number systems; 0.8 micron; 10 bit; 2 mA; 2.7 V; CMOS technology; RSD coded pipeline A/D-converter; active chip area; comparator offsets; current consumption; gain factor; interleaved pipeline structure; operational amplifier; power consumption; power saving scheme; redundant signed digit; CMOS technology; Capacitors; Circuits; Clocks; Energy consumption; Operational amplifiers; Output feedback; Pipelines; Sampling methods; Voltage;
Conference_Titel :
Analog and Mixed IC Design, 1996., IEEE-CAS Region 8 Workshop on
Conference_Location :
Pavia
Print_ISBN :
0-7803-3625-9
DOI :
10.1109/AMICD.1996.569390
