Title :
High-k gate dielectrics for sub-100 nm CMOS technology
Author :
Lee, S.J. ; Lee, C.-H. ; Kim, Y.H. ; Luan, H.F. ; Bai, W.P. ; Jeon, T.S. ; Kwong, D.L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
In this paper, the materials and processing challenges for the fabrication of high-quality. ultra-thin (EOT<1 run) high-K gate stack for sub-100 nm CMOS technology are reviewed along with our recent results on CVD HfO2. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve thinnest EOT are discussed. Results are presented on thermal stability of high-K materials, and interfacial reactions of high-K/Si and high-K/gate electrode. We also discuss key factors that govern the conduction and degradation mechanisms in the high-K gate stack. Both poly-Si and metal nitrides are explored as possible gate electrode materials arid the upper thermal budget limit for such materials are discussed
Keywords :
CMOS integrated circuits; chemical vapour deposition; dielectric thin films; electrical conductivity; hafnium compounds; reviews; surface chemistry; thermal stability; 100 nm; CMOS technology; CVD; HfO2; Si; conduction mechanisms; degradation; gate electrode materials; high-k gate dielectrics; high-quality; interfacial reactions; metal nitrides; poly-Si; post-deposition processing; thermal budget; thermal stability; ultra-thin gate stack; CMOS process; CMOS technology; Conducting materials; Electrodes; Fabrication; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Inorganic materials; Robustness;
Conference_Titel :
Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-6520-8
DOI :
10.1109/ICSICT.2001.981482
