Plasma charging damage in deep-submicron CMOS technology and beyond

Author

Cheung, Kin P.

Author_Institution

Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA

Volume

1

fYear

2001

fDate

2001

Firstpage

315

Abstract

Plasma charging damage in CMOS technology is reviewed. The gate-oxide thickness dependent sensitivity to charging damage is examined. Ultra thin gate-oxide can tolerate low to moderate charging stress at room temperature better than thicker oxide, but not at elevated temperature. When the charging stress level is high, gate-oxide reliability degradation will result regardless the stress temperature. When high-k dielectric replaces SiO₂ as gate-dielectric, plasma charging damage should become very severe again

Keywords

CMOS integrated circuits; dielectric thin films; integrated circuit reliability; integrated circuit technology; plasma materials processing; reviews; surface charging; 20 C; SiO₂; charging damage; charging stress; deep-submicron CMOS technology; gate-oxide reliability degradation; gate-oxide thickness dependent sensitivity; high-k dielectric; plasma charging damage; review; room temperature; stress temperature; thin gate-oxide; CMOS technology; Conductors; Degradation; Plasma materials processing; Plasma sources; Plasma temperature; Stress; Temperature sensors; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6520-8

Type

conf

DOI

10.1109/ICSICT.2001.981484

Filename

981484