DocumentCode
2205877
Title
Multi-chip modules testing and DFT
Author
Zorian, Yervant ; Marzouki, Meryem
Author_Institution
AT&T Bell Labs., Princeton, NJ, USA
Volume
2
fYear
1995
fDate
13-16 Aug 1995
Firstpage
722
Abstract
Among the most challenging problems of the Multi-Chip Module (MCM) technology are achieving acceptable MCM assembly yields and meeting product qualify requirements. Both of these problems can be significantly reduced by adopting adequate testing approaches, which guarantee the quality of incoming bare (unpackaged) dies prior to module assembly, ensure the structural integrity and performance of the assembled MCMs, and help isolating defective parts prior to the repair process. This paper presents a structured testability approach that helps resolving the above problems. This approach can be adopted during MCM design and utilized during the manufacturing process
Keywords
boundary scan testing; built-in self test; design for testability; integrated circuit testing; multichip modules; production testing; DFT; MCM testing; multi-chip modules; structured testability approach; Assembly; Automatic testing; Built-in self-test; Circuit testing; Design for testability; Integrated circuit interconnections; Integrated circuit testing; Manufacturing processes; Packaging machines; Performance evaluation;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on
Conference_Location
Rio de Janeiro
Print_ISBN
0-7803-2972-4
Type
conf
DOI
10.1109/MWSCAS.1995.510191
Filename
510191
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