Design of a 10-bit 100 MSamples/s BiCMOS D/A converter

A 10-bit 100 MSamples/s current-steering D/A converter (DAC) has been designed and processed in a 0.8 μm BiCMOS process. The DAC is intended for applications using direct digital synthesis, and focus has been set on achieving a high spurious free dynamic range (SFDR). The main part of the DAC is a matrix of current cells. To reduce skew between the steering signals to the current cells, an emitter-coupled logic (ECL) flip-flop, clocked by a global ECL clock, is included in each current cell. A bipolar differential pair, steered by the differential output of the ECL flip-flop, is used in each current cell to steer the current. At a generated frequency of f_g≈0.3·f_s (f_s=100 MSamples/s), the simulated SFDR is larger than 60 dB. The DAC operates at 5 V, and has a power consumption of approximately 650 mW. The area of the chip-core is 2.2 mm×2.2 mm. Furthermore a measure to estimate the SFDR for the DAC based on short term simulations is presented. This measure seems to correspond very well with SFDR for long term simulations