A PRNG Circuit on PLD with Feature of Low-Power, High-Speed, and Various Generation of Random Number Sequence

Author

Sato, Tomoaki ; Kikuchi, Kazuhira ; Fukase, Masa-aki

Author_Institution

Hirosaki Univ., Aomori

fYear

2006

fDate

14-17 Nov. 2006

Firstpage

1

Lastpage

4

Abstract

The design of PLD (programmable logic devices) used for various applications needs both high-speed and low-power operation. One of the design methods suited to this requirement is wave-pipeline technique. In this paper, we describe the wave-pipelining of PLD-design. This is applied to PRNG (pseudo-random number generator) circuit that is a sequential circuit. According to the result of the gate level simulation, the waved-PRNG circuit contributes to speed-up and low-power operation. In addition, this circuit is able to easily generate various random number sequences by controlling the operation clock frequency

Keywords

frequency control; logic design; pipeline processing; programmable circuits; programmable logic devices; random number generation; random sequences; sequential circuits; PLD; PRNG; clock frequency control; gate level simulation; high-speed operation; low-power operation; programmable logic device design; pseudorandom number generator circuit; random number sequence; sequential circuit; wave-pipeline technique; Circuit simulation; Clocks; Delay effects; Design methodology; Frequency; Pipelines; Programmable logic devices; Random number generation; Registers; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2006. 2006 IEEE Region 10 Conference

Conference_Location

Hong Kong

Print_ISBN

1-4244-0548-3

Electronic_ISBN

1-4244-0549-1

Type

conf

DOI

10.1109/TENCON.2006.343789

Filename

4142464