Global-cell selection in a partitioning-based fitter for an application-specific EPLD device

Author

Chrzanowska-Jeske, Malgorzata ; Gao, Tongjun ; Coppola, Alan

Author_Institution

Dept. of Electr. Eng., Portland State Univ., OR, USA

Volume

2

fYear

1995

fDate

13-16 Aug 1995

Firstpage

773

Abstract

This paper presents a vertex ordering heuristic which speeds up the search process in the partitioning based fitting algorithm. The fitting algorithm maps sequential circuit onto a special application EPLD device, the CY7C361 from Cypress Semiconductor. The same approach can also be used for other EPLD and FPGA architectures. The vertex ordering heuristic decreases the search time from hours to seconds for more complex designs. The quality of results is not effected as the algorithm remains exact

Keywords

application specific integrated circuits; circuit layout CAD; logic CAD; logic partitioning; programmable logic devices; sequential circuits; Cypress Semiconductor CY7C361; application-specific EPLD device; exact algorithm; fitting algorithm; global-cell selection; logic synthesis; partitioning-based fitter; search process; sequential circuit; vertex ordering heuristic; Automata; Circuit synthesis; Combinational circuits; Field programmable gate arrays; Fitting; Ice; Logic devices; Partitioning algorithms; Routing; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on

Conference_Location

Rio de Janeiro

Print_ISBN

0-7803-2972-4

Type

conf

DOI

10.1109/MWSCAS.1995.510203

Filename

510203