Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications

The progress of manufacturing technology makes the integration of many cores on a single silica substrate possible, which is called chip multiprocessor (CMP). But how to design the fabric on chip is still in discussion. Based on the advantages of scalability, network on chip (NoC) is a promising solution to solve the on-chip interconnection problem. However, it is still a challenge when communications through wires dominate the performance. The network communications infrastructure (routing, adapters and wires, etc.) cost too much both in power consumption and die area. In this paper, we propose a novel on-chip structure with dynamic reconfiguration capability for I/O supported parallel application. Our motivation is to reduce the cost of chip areas greatly by dynamic reconfiguration of the network in NoC architecture under the conditions that I/O parallel applications can be supported and the performance can be optimized. In our design, I/O node will be obtained firstly and then the information of the spare processing elements (PE) near it. Finally, combined with the communication pattern of applications, wires will be reallocated and reconfigurated to create a virtual regionalized area. The experimental results show that we can get a certain level of optimization among chip area, communication efficiency and the performance of I/O supported parallel applications.