Interfacial barriers for the 100-nm node and beyond: key challenges and emerging strategies

Tailoring ultrathin (<5-nm-thick) interfacial barriers- a factor of ~5-to-10 thinner than the current ones- will be critical in order to fully reap the potential advantages of Cu/low-k technology in sub-100-nm devices. This paper provides an overview of the key challenges such as conformality, adhesion, and thermal stability, faced by conventional PVD/CVD techniques in obtaining such barriers. The collateral effects of currently used barriers and Cu interconnect reliability are described, and the need to understand the atomistic pathways of interfacial interactions and failure mechanisms are emphasized. The potential of newly emerging technologies such as atomic layer deposition (ALD), self-organized barrier formation through alloy segregation and interfacial interaction (e.g., from Cu-Mg alloys), and self-assembly of molecular layers are reviewed and evaluated from the viewpoints of barrier performance, process feasibility and integration