Simulation Acceleration for Dynamic Timing Analysis with Static Timing Analysis

Simulation for dynamic timing analysis (DTA) with the delay information is now the most time-cost step of VLSI design. Although recent years, static timing analysis (STA) is developed well for timing analysis and check, it is no use for such designs as multi-clock-domain designs, so the DTA can not be replaced. In the paper, we propose a STA based simulation acceleration methodology for such designs that STA can not work well. We simulate the design with the mixture of the delay information of some modules and others of no delay information, so that we can finish simulations in very shorter time. The time saved is depended on the design´s realization. In the Godson2´s work, we get a very good result that we finish the simulation in one-sixth time of ordinary method