Title :
A flexible data-interlacing architecture for full-search block-matching algorithm
Author :
Lai, Yeong-Kang ; Chen, Liang-Gee ; Lee, Yung-Pin
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on some cascading strategies, the same chips can be flexibly cascaded for different block sizes, search ranges, and pixel rates. In addition, the cascading chips can efficiently reuse data to decrease external memory accesses and achieve a high throughput rate. Our results demonstrate that the architecture with 2-D data-reuse is a flexible, low-pin-counts, high-throughput, and cascadable solution for full search block-matching algorithm
Keywords :
VLSI; computer vision; motion estimation; parallel architectures; cascading strategies; data-reuse; external memory accesses; flexible data-interlacing architecture; full search block-matching algorithm; pixel rates; search ranges; Broadcasting; Computer architecture; Motion estimation; Multiplexing; Parallel processing; Shift registers; Systolic arrays; Throughput; Two dimensional displays; Very large scale integration;
Conference_Titel :
Application-Specific Systems, Architectures and Processors, 1997. Proceedings., IEEE International Conference on
Conference_Location :
Zurich
Print_ISBN :
0-8186-7959-X
DOI :
10.1109/ASAP.1997.606816
