Efficient generation of tests for combinational CMOS circuits

An efficient method for generating test patterns that yield high fault coverage for combinational CMOS circuits is presented. The method´s efficiency is a consequence of its ability to select test patterns for stuck-off and stuck-on transistor faults simultaneously and its ability to generate test patterns that cover the common memory-inducing fault, without the need for a conditionally sequential logic description. The proposed method consists of three steps. First, a simple procedure converts the transistor description of the CMOS circuit into a combinational logic description that represents the design-specified functionality of every transistor gate node of the CMOS circuit. Second, the standard D algorithm is applied to the logic description using a reduced set of logical stuck-at-1 and stuck-at-0 faults. Third a procedure generates an effective, yet short sequence of the D-algorithm test patterns that covers all of the stuck-on and stuck-off transistor faults