On-line digital compensation of analog circuit imperfections for cascaded ΣΔ modulators

Multi-bit cascaded ΣΔ modulators are known to suffer from performance degradation caused by analog circuit imperfections. In this paper, a method is introduced for the adaptive digital on-line compensation of linear errors, such as finite op-amp gain and capacitor mismatch. The method is discussed by considering a two-stage 3^rd -order multi-bit switched-capacitor modulator. Simulations show that nearly perfect compensation can be achieved with only slightly increased hardware complexity. Realizing the considered modulator without digital compensation would require at least 80 db op-amp gain and capacitor accuracy better than 0.05%, and comparably difficult specifications on op-amp settling. The analog circuit requirements are relaxed by the adaptation to 54 dB op-amp gain, 0.4% capacitor accuracy and 1% op-amp settling, which are readily attainable