A multiplier-free structure for 1-bit high-order digital delta-sigma modulators

A method and structure are presented for designing and realizing multiplier-free high-order 1-bit digital delta-sigma modulators for lowpass signals. A proven method incorporating empirical knowledge of stability is used to obtain the desired functionality. A close approximation of it is realized by a Lossless Discrete Integrator (LDI) ladder with powers-of-two coefficients and for which the Signal-Transfer Function (STF) is strictly unity. The major hardware requirements for a modulator of order N are 3N adders/subtractors and N registers. The resulting designs achieve close to the maximum possible performances reported in the literature. A 4^th-order, 16-times oversampled Field-Programmable Gate Array (FPGA) prototype displays an inband noise power level of -55 dB. Simulation of a modulator of order 6 and OSR set to 100 yields a 130 dB SNR