Study of direct-tunneling gate oxides for CMOS applications

Author

Momose, Hisayo Sasaki ; Nakamura, Shin-ichi ; Katsumata, Yasuhiro ; Iwai, Xrosh

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1998

fDate

4-5 Jun 1998

Firstpage

30

Lastpage

33

Abstract

Progress in MOS LSIs has continued for over 25 years through a process of MOSFET downsizing. Along with downsizing of MOSFETs, gate oxide thickness continues to be reduced. Recently proposed direct tunneling gate oxide MOSFETs show a good possibility for achieving extremely high drive currents (Momose et al., 1994, 1996, 1997; Lo et al., 1997; Timp et al., 1997). In this paper, it is shown that ultra-thin gate oxides beyond the tunneling limit can be applicable to MOSFETs and that extremely high DC and AC performances are realized. The hot-carrier reliability and oxide breakdown voltage of these MOSFETs are also compared with those of thicker oxide cases

Keywords

CMOS integrated circuits; MOSFET; dielectric thin films; electric breakdown; hot carriers; integrated circuit reliability; integrated circuit testing; large scale integration; tunnelling; AC performance; CMOS applications; DC performance; MOS LSIs; MOSFET downsizing; MOSFETs; SiO₂-Si; direct tunneling gate oxide MOSFETs; direct-tunneling gate oxides; drive currents; gate oxide thickness; gate oxide tunneling limit; hot-carrier reliability; oxide breakdown voltage; ultra-thin gate oxides; Capacitance; Doping; Electrodes; FETs; Hot carriers; MOSFET circuits; Oxidation; Rapid thermal annealing; Solids; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Plasma Process-Induced Damage, 1998 3rd International Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

0-9651577-2-5

Type

conf

DOI

10.1109/PPID.1998.725567

Filename

725567