Title :
The 4-Phase Frame Partitioning Circuit
Author_Institution :
R&D Dept., Phasetronic Labs., Athens
Abstract :
The behavior of the 4-phase frame partitioning (FPT4) circuit is analyzed. The circuit performs the phase partitioning of the input clock signal into one out of fifteen available partitions for a given four-phase frame. Each partition is being selectable by a 4-bit control word. A phase difference equal to the half period of the clock signal is used internally to achieve the correct pulse timing of the output signals. The VHDL description of the FPT4 cell is given and the simulation and synthesis results are presented
Keywords :
automatic test pattern generation; clocks; design for testability; logic partitioning; 4 bit; 4-phase frame partitioning circuit; automatic test pattern generation; clock signal; control word; design for testability; phase difference; pulse timing; Circuits; Clocks; Frequency; Laboratories; Research and development;
Conference_Titel :
Microelectronics, 2006 25th International Conference on
Conference_Location :
Belgrade
Print_ISBN :
1-4244-0117-8
DOI :
10.1109/ICMEL.2006.1650985
