Modeling and Simulation of Submicron MOSFETs with Alternative Gate Dielectrics for DRAM Cells

In this study, we designed and simulated MOS devices having alternative gate dielectrics and examined their electrical behaviour as well as their effectiveness on the performance of a DRAM cell containing them. The devices under test had gate dielectrics of SrTiO₃, (Ba_1-xSr_x)TiO₃, TiO₂, Ta₂O₅, Y₂O₃ and (Pb₁ La_x)TiO₃. Equivalent oxide thicknesses were derived between 0.95 and 4 nm. Among the candidate materials, SrTiO₃ was the most promising when data retention is required, while Y₂O₃ depicted the best I-V behavior. An increased cell capacitance resulted to higher memory refreshing times, improving substantially the device reliability