Title :
Tiling with limited resources
Author :
Calland, P.-Y. ; Dongarra, Jack ; Robert, Yves
Author_Institution :
LIP, Ecole Normale Superieure de Lyon, France
Abstract :
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to the mapping and scheduling of the tiles on to physical processors. We present several new results in the context of limited computational resources, and assuming communication-computation overlap. In particular, under some reasonable assumptions, we derive the optimal mapping and scheduling of tiles to physical processors
Keywords :
data structures; digital arithmetic; performance evaluation; processor scheduling; communication-computation overlap; computational resources; optimal mapping; perfect loop nests; physical processors; scheduling; source-to-source program transformation; tiling; uniform dependences; Arithmetic; Context; Contracts; Distributed computing; Electronic mail; Laboratories; Lifting equipment; Network address translation; Processor scheduling; Tiles;
Conference_Titel :
Application-Specific Systems, Architectures and Processors, 1997. Proceedings., IEEE International Conference on
Conference_Location :
Zurich
Print_ISBN :
0-8186-7959-X
DOI :
10.1109/ASAP.1997.606829
