Effects of NO Annealing on the Characteristics of GaN MIS Capacitor

An ultra-thin thermally-grown GaO_xN_y was formed between deposited SiO₂ dielectric and GaN wafer to improve the interface quality. The interface-trap density at 0.4 eV below the conduction-band edge was reduced by one order compared with that of a sample without the stacked GaO_xN_y. NO annealing was conducted on both SiO₂/ GaN and SiO₂/GaO_xN_y/GaN MIS structures, and turned out to effectively suppress the oxide charges. The sample with stacked GaO_xN_yannealed in NO achieved the lowest oxide-charge density (Q_ox) of 1.7times10¹¹cm² eV^-1; Q_ox of the one without stacked GaO_xN_y annealed in NO was 9.5 times10¹¹cm² eV^-1; those samples not annealed in NO got high Q_ox of 8times10¹² cm² eV^-1, with or without stacked GaO_x N_y. Moreover, NO annealing was found to effectively reduce border traps. The interface quality was improved on both the sample with the GaO_xN_y interlayer annealed in nitrogen and the non-stacked sample annealed in NO. The breakdown field and leakage current of the gate dielectrics were also compared in this work