Title :
Rapid in-line characterization of plasma-induced damage on a 0.25 μm CMOS ASIC technology
Author :
Liang, V. ; Bothra, S. ; Sur, H. ; Sengupta, S.
Author_Institution :
VLSI Technol. Inc., San Jose, CA, USA
Abstract :
An investigation into CMOS gate oxide failures during the process development of an advanced 0.25μm CMOS ASIC process is presented. Using a SEM technique called passive voltage contrast (PVC), specific backend process steps contributing to the failures were rapidly identified as titanium deposition and SiN deposition. Both these processes are plasma based processes and the failures were addressed by applying a basic understanding of plasma charging induced damage mechanisms. This case study demonstrates the value of PVC in the rapid in-line characterization of gate oxide integrity, and in facilitating quick-turn isolation and elimination of the sources of damage
Keywords :
CMOS integrated circuits; application specific integrated circuits; dielectric thin films; failure analysis; integrated circuit testing; integrated circuit yield; plasma CVD; production testing; scanning electron microscopy; surface charging; surface contamination; 0.25 micron; CMOS ASIC process; CMOS ASIC technology; CMOS gate oxide failure; HDP-CVD; SEM technique; Si; SiN deposition; SiN-SiO2; SiO2-Si; Ti-SiO2; damage source elimination; gate oxide integrity; passive voltage contrast SEM technique; plasma based processes; plasma charging induced damage mechanisms; plasma-induced damage; process development; quick-turn damage source isolation; rapid in-line characterization; titanium deposition; Application specific integrated circuits; CMOS process; CMOS technology; Metallization; Plasma density; Plasma materials processing; Plasma measurements; Plasma sources; Routing; Testing;
Conference_Titel :
Plasma Process-Induced Damage, 1998 3rd International Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
0-9651577-2-5
DOI :
10.1109/PPID.1998.725596
