Total dose radiation experiments in CMOS/SOI 4 Kb SRAM

Author

Yunlong, Liu ; Xinyu, Liu ; Chaohe, Hai ; Haifeng, Sun ; Zhengsheng, Han ; He, Qian

Author_Institution

Microelectron. R&D Center, Acad. Sinica, Beijing, China

Volume

1

fYear

2001

fDate

2001

Firstpage

676

Abstract

This paper describes the total dose radiation performance of CMOS/SOI 4 Kb SRAMs fabricated in a radiation hardened partially depleted SOI CMOS technology. The SRAM adopts 1 K×4 architecture. It achieves a fast access time 30 ns and chip size 3.6 mm×3.84 mm. Memory functionality does well after a total dose irradiation up to 5×10⁵ rad(Si) under 3 V power supply. This meets the needs in military and aerospace fields. It is the first time that the radiation effects on SOI VLSI were investigated in China

Keywords

CMOS memory circuits; SRAM chips; VLSI; gamma-ray effects; military avionics; radiation hardening (electronics); silicon-on-insulator; space vehicle electronics; 3 V; 30 ns; 4 Kbit; CMOS SOI SRAM; VLSI; aerospace use; fast access time; function tests; gamma irradiation; memory functionality; military use; radiation hardened partially depleted technology; six-transistor memory cell; total dose radiation performance; CMOS technology; Circuits; Decoding; Fabrication; Isolation technology; Microelectronics; Power supplies; Radiation effects; Radiation hardening; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6520-8

Type

conf

DOI

10.1109/ICSICT.2001.981569

Filename

981569