Title :
Local Sealing of High Aspect Ratio Vias for Single Step Bottom-up Copper Electroplating of Through Wafer Interconnects
Author :
Saadaoui, M. ; Wien, W. ; Zeijl, H.V. ; Schellevis, H. ; Laros, M. ; Sarro, P.M.
Author_Institution :
Delft Univ. of Technol., Delft
Abstract :
This paper presents a novel technology for copper electroplating in high aspect ratio silicon vias. The described approach is based on the bottom-up technology with the use of a new specifically designed electroplating holder for local sealing and filling of the vias. The technological steps are described and demonstrated for 20mum wide vias with an aspect ratio of 15. Moreover, a simplified simulation model is presented in order to explain the local sealing phenomenon and the subsequent electroplating.
Keywords :
electroplating; integrated circuit interconnections; integrated circuit modelling; wafer-scale integration; bottom up technology; copper electroplating; electroplating holder; high aspect ratio; local sealing; simulation model; single step bottom up copper; size 20 mum; wafer interconnects; Copper; Electronic components; Etching; Fabrication; Filling; Integrated circuit interconnections; Packaging; Resists; Silicon; Wafer bonding;
Conference_Titel :
Sensors, 2007 IEEE
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-1261-7
Electronic_ISBN :
1930-0395
DOI :
10.1109/ICSENS.2007.4388566
