Title :
A scalable systolic array architecture for the 2D discrete wavelet transform
Author :
Chen, Jijun ; Bayoumi, Magdy A.
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Abstract :
Summary form only given, as follows. A systematic synthesis approach has been applied to the 2D discrete wavelet transform (DWT), and a scalable systolic array architecture has been derived based on the data dependence analysis and linear index space transformation. The architecture has regular topology, local routing, simple controller and high throughput rate, and it can be easily extended to different parameters of various levels, macroblocks and filters. The architecture has been implemented on Cadence Edge Framework
Keywords :
network routing; network topology; systolic arrays; transforms; wavelet transforms; 2D discrete wavelet transform; Cadence Edge Framework; data dependence analysis; linear index space transformation; local routing; macroblocks; scalable systolic array architecture; throughput rate; topology; Computer architecture; Data analysis; Discrete wavelet transforms; Filters; Routing; Systolic arrays; Throughput; Topology; Wavelet analysis;
Conference_Titel :
Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
0-7803-2972-4
DOI :
10.1109/MWSCAS.1995.510290
