Clocking Challenges in High Speed Source Synchronous Interfaces

The challenges in clocking high speed interfaces such as the communication between multi micro-processor systems or the communication between micro-processor and off-chip memory was introduced by our need for high data rate with low bit-error-rates (BER). Minimization of clock jitter is one of the main challenges in making the high data rate links work. There are a series of issues affecting clock jitter that must be brought to adequate levels in order for a particular data rate communication with a desired BER to be successful. The main noise sources affecting clock jitter can be grouped into two main categories. The first category would be the noise sources that are random in nature, such as the MOS device thermal and flicker noise. These sources generally affect the clock generation circuits such as phase locked loops (PLL). Naturally, the second category would contain noise sources and effects causing clock jitter that are more deterministic. In this category we would generally put the effects on the clock jitter caused by the power supply noise, PLL charge pump (CP) feed-through, and off-chip channel effects