An overview of the Alpha AXP 21164 microprocessor

Author

Benschneider, Brad

Author_Institution

Digital Equip. Corp., USA

Volume

2

fYear

1995

fDate

13-16 Aug 1995

Firstpage

1131

Abstract

This paper describes the microarchitecture of the Alpha 21164 microprocessor, a second-generation, custom VLSI, 64-bit implementation of the Alpha architecture. The chip is designed in a 0.5 um CMOS technology, contains 9.3 M transistors, operates at 3.3 V, and is designed for a typical operating frequency of 300 MHz. It contains an 8-Kbyte instruction cache; an 8-Kbyte, dual-ported data cache; and a 96-Kbyte, unified, second level, 3-way set associative, fully pipelined, write-back cache. The chip can issue up to four instructions per cycle, contains two 64-bit integer pipelines and two 64-bit floating-point pipelines; and implements a high-throughput memory subsystem that can support multiprocessing systems. The chip delivers 1200-MIPS/600-MFlops (peak), and SPECint92/SPECfp92 performance of 343/512, respectively. Several attributes of the microarchitecture needed to attain this performance are discussed

Keywords

CMOS digital integrated circuits; VLSI; computer architecture; microprocessor chips; pipeline processing; 0.5 micron; 1200 MIPS; 3.3 V; 300 MHz; 600 MFLOPS; 64 bit; Alpha AXP 21164 microprocessor; CMOS technology; associative pipelined write-back cache; dual-ported data cache; floating-point pipeline; instruction cache; integer pipeline; memory subsystem; microarchitecture; multiprocessing system; second-generation custom VLSI; CMOS technology; Frequency; Logic; Microarchitecture; Microprocessors; Multiprocessing systems; Operating systems; Performance gain; Pipelines; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1995., Proceedings., Proceedings of the 38th Midwest Symposium on

Conference_Location

Rio de Janeiro

Print_ISBN

0-7803-2972-4

Type

conf

DOI

10.1109/MWSCAS.1995.510295

Filename

510295