Approach to Partially Self-Checking Finite State Machine Design

This paper presents a cost-effective technique of partially self-checking finite state machine (FSM) design. The proposed technique is similar to duplication with comparison, wherein duplicated combinational logic (CL) block of the FSM and comparator act as a function checker that detects any erroneous response of the original CL block. However, instead of realizing checker with full error-detection capability, we select a subset of checker´s inputs to implement partial, but simplified function checker. Effectiveness of the technique is evaluated on a set of MCNC 91 benchmark sequential circuits