Systematic design of novel architectures for implementation of Radon Transform

A systematic methodology is introduced for designing highly pipelined array architectures for implementation of Discrete Radon Transform and its Inverse, starting from the algorithmic level and ending with the architectural (hardware) level. Due to large amount of data, the original algorithm is partitioned into nested loops that can be easily mapped onto fixed-size hardware. The proposed methodology derives a plethora of alternative architectures, which meet various parameters such as high-throughput rate, maximum hardware utilization, and pipelinability. Moreover, the derived architectures are piecewise regular and consist of linear and/or 2-D systolic arrays