Performance analysis and design of wideband CMOS voltage controlled ring oscillator

A wide band two stage CMOS voltage controlled ring oscillator (VCRO) based on fully differential delay cells proposed by Yan and Luong has been analyzed. The two stage and three stage VCO circuits are realized using GPDK 90 nm CMOS technology. The design parameters are varied widely and performance of the circuit is evaluated in this work. This scaled VCO has a very wide operating frequency range from 1.22 GHz to 3.22 GHz, which corresponds to a tuning range of 62.11%. Its power consumption is 9.61 mW and the phase noise is about - 90.01 dBc/Hz at 600 kHz offset from 1.74 GHz. The phase noise of the differential VCO is improved by cascading more number of stages at the cost of more power consumption. Three-stage differential delay VCO is implemented and it is observed to achieve - 95.47dBc/Hz of phase noise which is about 6 dB better than the two stage case with better tuning range of 64.23%. However the power consumption of the circuit increases to 14.44 mW.