Abstract :
Notice of Violation of IEEE Publication Principles
"A -85dBc Reference Spurs Quadratude 1-2.5GHz Dual-Path Sampled Loop Filter CMOS PLL with sub-1??rms Phase Noise"
by Maxim, A.; Gheorghe, M.;
in the 2006 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. San Francisco, CA, 2006
After careful and considered review, it has been determined that the above paper is in violation of IEEE\´s Publication Principles.
Specifically, the coauthor\´s name was fabricated by Adrian Maxim and added to the paper. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:
C. Turinici, D. Smith, S. Dupue, M. Gheroge, R. Johns, D. Antrik
Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.
Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.
Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A wide tuning range multi-GHz frequency synthesizer was realized in a 0.13mum CMOS process using a dual-path sampled loop filter. Both the integral and proportional loop filter paths use sample and hold switched capacitor circuits that completely isolate the oscillator from the charge-pump switching action. A sub-1degrms integrated phase noise was achieved by using a large amplitude Pierce crystal oscillator with a current starved squaring buffer, in conjunction with a low gain ring oscillator. A multi-regulator PLL architecture using series and shunt regulators was implemented to minimi- e the supply spurs and noise injection. PLL specifications include: 1-2.5GHz frequency range, 5-20MHz channel separation, 0.5-2MHz loop bandwidth, <-85dBc reference spurs, <100mA current from a 2.5V supply and 1000times400mum2 die area
Keywords :
CMOS integrated circuits; UHF integrated circuits; crystal oscillators; digital filters; phase locked loops; sample and hold circuits; switched capacitor networks; 0.13 micron; 1 to 2.5 GHz; 100 mA; 2.5 V; CMOS phase locked loop; Pierce crystal oscillator; charge-pump switching action; current starved squaring buffer; dual-path sampled loop filter; frequency synthesizer; multiregulator PLL architecture; phase noise; reference spurs; ring oscillator; sample and hold circuits; series regulators; shunt regulators; switched capacitor circuits; Circuit optimization; Filters; Frequency synthesizers; Notice of Violation; Phase locked loops; Phase noise; Radiofrequency integrated circuits; Ring oscillators; Tuning;
