A dual-band four-mode /spl Delta/-/spl Sigma/ frequency synthesizer

Author

Chen, Wei-Zen ; Yu, Dai-Yuan

Author_Institution

Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu

fYear

2006

fDate

11-13 June 2006

Abstract

This paper describes the design of a dual-band, four-mode Delta-Sigma frequency synthesizer for WLAN a,b,g and Bluetooth applications. Integrating both a multi-modulus PLL and a 3^rd order Delta-Sigma modulator in a single chip, the channel spacing of the RF synthesizer can be as low as 20 kHz and the frequency hopping time is less than 67 musec. A charge pump circuit is proposed to improve its linearity and the matching of the pumping currents. The measured phase noise at 1MHz offset are about -114 dBc/Hz and -116 dBc/Hz respectively at 5 GHz and 2.5 GHz frequency bands. Fabricated in a 0.18-mum CMOS process, the chip size is 1.95 mm². The total power consumption is 19.54 mW from a 1.8 V power supply

Keywords

Bluetooth; UHF integrated circuits; frequency synthesizers; integrated circuit design; microwave integrated circuits; phase locked loops; sigma-delta modulation; wireless LAN; 0.18 micron; 1.8 V; 19.54 mW; 2.5 GHz; 5 GHz; Bluetooth; CMOS process; Delta-Sigma modulator; RF synthesizer; WLAN applications; channel spacing; charge pump circuit; frequency synthesizer; multimodulus phase locked loop; phase noise; Bluetooth; Channel spacing; Charge pumps; Circuits; Delta modulation; Dual band; Frequency synthesizers; Phase locked loops; Radio frequency; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-9572-7

Type

conf

DOI

10.1109/RFIC.2006.1651125

Filename

1651125