DocumentCode
2210146
Title
Measuring 6D Chip Alignment in Multi-Chip Packages
Author
Chow, Alex ; Hopkins, David ; Ho, Ron ; Drost, Robert
Author_Institution
VLSI Res. Group, Menlo Park
fYear
2007
fDate
28-31 Oct. 2007
Firstpage
1307
Lastpage
1310
Abstract
We present techniques to detect all six degrees of positioning of one CMOS chip relative to another using capacitance measurements. Unlike other capacitive sensing schemes, these solutions achieve sub-femofarad resolution by directly measuring coupling capacitance and rejecting parasitic capacitances. We apply these techniques to dynamically monitor the 6D alignment of chips in multi-chip packages.
Keywords
CMOS integrated circuits; capacitance measurement; capacitive sensors; multichip modules; 6D chip alignment; CMOS chip; capacitance measurements; capacitive sensing schemes; coupling capacitance; multi chip packages; sub femofarad resolution; CMOS technology; Capacitance measurement; Coupling circuits; Electronics packaging; Monitoring; Parasitic capacitance; Position measurement; Semiconductor device measurement; Sensor systems; Spatial resolution;
fLanguage
English
Publisher
ieee
Conference_Titel
Sensors, 2007 IEEE
Conference_Location
Atlanta, GA
ISSN
1930-0395
Print_ISBN
978-1-4244-1261-7
Electronic_ISBN
1930-0395
Type
conf
DOI
10.1109/ICSENS.2007.4388650
Filename
4388650
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