An experimental soft-error immune 64-Kb 3 ns ECL bipolar RAM

Author

Yamaguchi, Kazuhiro ; Nanbu, Hiroaki ; Kanetani, Kazuo ; Homma, Noriyuki ; Nakamura, Tohru ; Ohhata, Kenichi ; Uchida, Akihisa ; Ogiue, Katsumi

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1988

fDate

12-13 Sep 1988

Firstpage

26

Lastpage

27

Abstract

An experimental soft-error immune 64-kb 3-ns emitter couple logic (ECL) random access memory (RAM) has been developed. Its key factors are: a soft-error immune memory cell, an upward transistor decoder, a Darlington word driver with advanced discharge circuits, and 0.8 μm SICOS technology. To reduce the memory cell size, double-layer polysilicon is used for high and low load-resistor. These double layers of polysilicon are essential in realizing the memory cell size of 498 μm²

Keywords

bipolar integrated circuits; emitter-coupled logic; integrated memory circuits; random-access storage; 0.8 micron; 3 ns; 64 kbit; Darlington word driver; ECL bipolar RAM; SICOS technology; discharge circuits; double-layer polysilicon; soft error immunity; soft-error immune memory cell; upward transistor decoder; Capacitance; Clamps; Decoding; Delay; Driver circuits; Laboratories; Random access memory; Read-write memory; Transistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1988., Proceedings of the 1988

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1988.51037

Filename

51037