Title :
3-Dimensional Integration for Interconnect Reduction in for Nano-CMOS Technologies
Author :
Chan, Mansun ; Zhang, Shengdong ; Lin, Xinnan ; Wu, Xusheng ; Chan, Philip C.H.
Author_Institution :
Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol.
Abstract :
This paper describes a method to integrate non-planar multi-gate CMOS devices in the third dimension. The technology is based on highly scalable multi-gate MOSFET structures which are promising for nano-scale integration. The extension to have active devices placed the third dimension allow significant reduction in the interconnect loading. We have demonstrated the potential of such technology though experimentally fabricated devices as well as detail system level analysis
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit interconnections; nanotechnology; active device; device fabrication; interconnect loading reduction; multigate MOSFET structure; nanoscale integration; nonplanar CMOS device; CMOS technology; Etching; Fabrication; Implants; Integrated circuit interconnections; Integrated circuit technology; Inverters; MOSFET circuits; Technological innovation; Three-dimensional integrated circuits;
Conference_Titel :
TENCON 2006. 2006 IEEE Region 10 Conference
Conference_Location :
Hong Kong
Print_ISBN :
1-4244-0548-3
Electronic_ISBN :
1-4244-0549-1
DOI :
10.1109/TENCON.2006.343731
