Flexible low-complexity decoding architecture for QC-LDPC codes

A novel flexible decoding architecture for quasi-cyclic (QC) low-density parity-check (LDPC) code is proposed in this paper to reduce decoding complexity. The novelty of this architecture lies in a new time-sharing scheme of processing units, which provides low complexity and flexible serial factor of decoding hardware. Without loss of coding performance, the architecture requires significantly less processing units compared with known semi-parallel decoders at the expense of throughput decrease, while keeping memory requirement unchanged. As demonstrated by hardware and software implementation results, the proposed architecture is advisable and competent for wireless mobile systems and portable devices.