Title :
An approximate timing analysis method for datapath circuits
Author :
Yalcin, H. ; Hayes, J.P. ; Sakallah, K.A.
Author_Institution :
Adv. Comput. Archit. Lab., Michigan Univ., Ann Arbor, MI, USA
Abstract :
We present a novel timing analysis method ACD that computes an approximate value for the delay of datapath circuits. Based on the conditional delay matrix (CDM) formalism we introduced earlier the ACD method exploits the fact that most datapath signals are directed by a small set of control inputs. The signal propagation conditions are restricted to a set of predefined central inputs, which results in significant reductions in the size of the conditions as well as computation time. We have implemented ACD and experimented with reverse-engineered high-level versions of the ISCAS-85 benchmarks. Our results demonstrate up to three orders of magnitude speedup in computation time over exact methods, with little or no loss in accuracy.
Keywords :
combinational circuits; delays; logic CAD; logic testing; ACD; ISCAS-85 benchmarks; approximate timing analysis method; computation time; conditional delay matrix; datapath circuits; delay; reverse-engineered high-level versions; signal propagation conditions; Circuit analysis computing; Computer architecture; Data analysis; Delay effects; Electronic mail; Laboratories; Logic circuits; Propagation delay; Size control; Timing;
Conference_Titel :
Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-8186-7597-7
DOI :
10.1109/ICCAD.1996.569410
