• DocumentCode
    2211301
  • Title

    Cost competitive PI-SI co-design for DDR interfaces

  • Author

    Cai, Kinger Xingjian ; Ji, Steven Yun

  • Author_Institution
    Intel Corporation, Santa Clara, CA, United States
  • fYear
    2015
  • fDate
    16-22 Aug. 2015
  • Firstpage
    645
  • Lastpage
    649
  • Abstract
    The total DDR on-die AC power delivery noise can be decomposed into high pass filtered (HPF) Vppa and low pass filtered (LPF) Vppb. PI-SI co-simulation reveals that Vppa impacts timing (eye width) and Vppb impacts signal voltage amplitude (eye height), and they need to be budgeted in different manner. Consequently the Power Delivery Network (PDN) is optimized with significant Cpkg and Cdie reduction for a small form factor while maintaining the reliable SI performance, which is demonstrated with a DDR interface and correlated with lab measured data on a particular SoC platform.
  • Keywords
    Capacitance; Correlation; Noise; Resonant frequency; Silicon; System-on-chip; Timing; Burst-Idle-Burst (BIB); DDR; PI-SI co-simulation; Power Delivery Network (PDN); correlation; small Form Factor;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electromagnetic Compatibility (EMC), 2015 IEEE International Symposium on
  • Conference_Location
    Dresden, Germany
  • Print_ISBN
    978-1-4799-6615-8
  • Type

    conf

  • DOI
    10.1109/ISEMC.2015.7256239
  • Filename
    7256239