Title :
High linearity performance of 0.13 /spl mu/m CMOS devices using field-plate technology
Author :
Wei, Chien-Cheng ; Chiu, Hsien-Chin ; Feng, Wu-Shiung
Author_Institution :
Dept. of Electron. Eng., Chang Gung Univ., Taoyuan
Abstract :
High linearity performance of 0.13 mum CMOS devices using field-plate technology is presented in this paper. The field-plate technology functions for reducing the electric field between gate and drain terminals, which provides a field-plate induced depletion region and decreases the leakage current to greatly improve the linearity and power performance of CMOS devices. The third-order inter-modulation product (IM3) of 0.13 mum NMOS devices with and without field-plate technology are -41.8 dBm and -32.4 dBm for input power is -10 dBm, respectively. The experimental results show that the field-plate architecture is more effective to exhibit high linearity and power for CMOS RFIC applications
Keywords :
MOSFET; leakage currents; semiconductor device reliability; 0.13 micron; CMOS devices; NMOS devices; electric field reduction; field-plate technology; leakage current; radiofrequency integrated circuits; third-order intermodulation product; CMOS process; CMOS technology; Dielectric devices; Electrons; HEMTs; Linearity; MODFETs; MOS devices; Radiofrequency integrated circuits; Voltage;
Conference_Titel :
Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-9572-7
DOI :
10.1109/RFIC.2006.1651194
