A 3GHz subthreshold CMOS low noise amplifier

Author

Lee, Hanil ; Mohammadi, Saeed

Author_Institution

Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN

fYear

2006

fDate

11-13 June 2006

Abstract

This paper presents an integrated 3GHz ultra low power CMOS low noise amplifier (LNA) based on a cascode topology where both MOS transistors are biased in subthreshold region. At 160muW DC power consumption and power supply of 0.6V, this LNA has a measured power gain of 4.5dB and noise figure of 6.3dB. At 400muW power consumption, the LNA delivers a power gain of 9.1dB and a noise figure of 4.7dB. The measured IIP3 under 400uAV power dissipation is -11dBm while the input and output matching is better than -13dB. By using a figure of merit that contains the effect of amplifier noise figure, gain, linearity, DC power consumption and operating frequency, we have shown that this amplifier is superior to conventional CMOS LNA designs reported in the literature

Keywords

CMOS integrated circuits; MMIC amplifiers; low noise amplifiers; network topology; 0.6 V; 3 GHz; 4.5 dB; 4.7 dB; 6.3 dB; 9.1 dB; CMOS low noise amplifier; MOS transistors; amplifier noise figure; cascode topology; subthreshold region; Energy consumption; Gain measurement; Low-noise amplifiers; MOSFETs; Noise figure; Noise measurement; Power amplifiers; Power measurement; Power supplies; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-9572-7

Type

conf

DOI

10.1109/RFIC.2006.1651199

Filename

1651199